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benefits and features ? completely manages all timekeeping functions o real - time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap - year compensation valid up to 2100 o 3 1 x 8 battery - backed general - purpose ram ? simpl e serial port interfaces to most microcontrollers o simple 3 - wire interface o ttl - com patible (v cc = 5v) o single - byte or multiple - byte (burst mode) data transfer for read or write of clock or ram data ? low power operation extends battery backup run time o 2 .0v to 5.5v full operation o u ses less than 300na at 2.0v ? 8- pin dip an d 8 - pin so minimizes required space ? optional industrial temperature range: - 40c to +85c supports operation in a wide range of applications ? underwriters laboratories ? (ul) recognized pin configurations ordering information part temp range pin - package top mark* ds1302+ 0c to +70c 8 pdip (300 mils) ds1302 ds1302n+ - 40c to +85c 8 pdip (300 mils) ds1302 ds1302s+ 0c to +70c 8 so (208 mil s) ds1302s ds1302sn+ - 40c to +85c 8 so (208 mils) ds1302s ds1302z+ 0c to +70c 8 so (150 mils) ds1302z DS1302ZN+ - 40c to +85c 8 so (150 mils) DS1302ZN +denotes a lead - free/rohs - compliant package. *an n anywhere on the top mark indicates an industrial temperature grade device. a + anywhere on t he top mark indicates a lead - free device. ul is a registered trademark of underwriters laboratories, inc. ds1302 trickle - charge timekeeping chip v cc1 sclk i/o ce v cc2 x1 x2 gnd 8 7 6 5 1 2 3 4 dip ( 300 mils ) ds1302 v cc2 x1 x2 gnd v cc1 sclk i/o ce 8 7 6 5 1 2 3 4 so (208 mils/150 mils) ds1302 top view 1 of 13 rev: 3/15 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p detailed description the ds1302 trickle - charge timekeeping chip contains a real - time clock/calendar and 31 bytes of static ram. it communicates with a microprocessor via a simple serial interface. the real - time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in eit her the 24 - hour or 12 - hour format with an am/pm indicator. interfacing the ds1302 with a microprocessor is simplified by using synchronous serial communication. only three wires are required to communicate with the clock/ram: ce, i/o (data line), and sclk (serial clock). data can be transferred to and from the clock/ram 1 byte at a time or in a burst of up to 31 bytes. the ds1302 is designed to operate on very low power and retain data and clock information on less than 1 w. the ds1302 is the successor to the ds1202. in addition to the basic timekeeping functions of the d s1202, the ds1302 has the additional features of dual power pins for primary and backup power supplies, program mable trickle charger for v cc1 , and seven additional bytes of scratchpad memory. operation figure 1 shows the main elements of the serial timekeeper: shift register, control log ic, oscillator, r eal - time clock, and ram. typical operating circuit ds1302 cpu v cc v cc2 sclk ce gnd x2 x1 v cc i/o v cc1 2 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p figure 1 . block diagram typical operating characteristics (v cc = 3.3v, t a = +25c, unless otherwise noted.) 3 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p pin des cription pin name function 1 v cc2 primary power - supply pin in dual supply configuration. v cc1 is connected to a backup source to maintain the time and date in the absence of primary power. the ds1302 operates from the larger of v cc1 or v cc2 . when v cc2 is greater than v cc1 + 0.2v, v cc2 powers the ds1302. when v cc2 is less than v cc1 , v cc1 powers the ds1302. 2 x1 connections for standard 32.768khz quartz crystal. the internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pf. for more information on crystal selection and crystal layout considerations, refer to application note 58: crystal considerations for dallas real - time clocks . the ds1302 can also be driven by an external 32.768khz oscillator. in this configura tion, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. 3 x2 4 gnd ground 5 ce input. ce signal must be asserted high during a read or a write. this pin has an internal 40k ? (typ) pulldown resistor to ground. note: previous data sheet revisions referred to ce as rst . the functionality of the pin has not changed. 6 i/o input/push - pull output. the i/o pin is the bidirectional data pin for the 3 - wire interface. this pin has an internal 40k ? (typ) pulldown resistor to gro und. 7 sclk input. sclk is used to synchronize data movement on the serial interface. this pin has an internal 40k ? (typ) pulldown resistor to ground. 8 v cc1 low - power operation in single supply and battery - operated systems and low - power battery backup. in systems using the trickle charger, the rechargeable energy source is connected to this pin. ul recognized to ensure against reverse charging current when used with a lithium battery. go to www.maxim - ic.com/techsupport/qa/ntrl.htm . 4 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p oscillator circuit the ds1302 uses an external 32.768khz crystal. the oscillator circuit does not requir e any external resistors or capacitors to operate. table 1 specifies several crystal parameters for the external crystal. figure 1 shows a functional schematic of the oscillator circuit. if using a crystal w ith the specified characteristics, the startup time is usually less than one second. clock accuracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accur acy of the match between the capacitive load of the oscillator circuit and the capacitive load for which t he crystal was trimmed. additional error will be added by crystal frequency drift caused by temperature shifts . external circuit noise coupled into the oscillator circuit may result in the clock running fast. figure 2 shows a typical pc board layout for isolating the crystal and oscillator from noise. refer to application note 58: crystal considerations for dallas real - time clocks for detailed information. table 1 . crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals . refer to application note 58: crystal considerations for dallas real - time clocks for additional specifications. figure 2 . typical pc board layout for crystal command byte figure 3 shows the command byte. a command byte initiates each data transfer. the ms b (bit 7) must be a logic 1. if it is 0, writes to the ds1302 will be disabled. bit 6 specifies clock/calendar data if logic 0 or ram data if logic 1. bits 1 to 5 specify the designated registers to be input or output, and the lsb (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. the command byte is always input starting with the lsb (bit 0). figure 3 . address/command byte local ground plane (layer 2) crystal x1 x2 gnd note: avoid routing signals in the crosshatched area (upper left - hand quadrant) of the package unless there is a ground plane between the signal line and the package. 1 ram ck a4 a3 a2 a1 a0 rd wr 7 6 5 4 3 2 1 0 5 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p ce and clock control driving the ce input high initiates all data transfers. the ce input serves two functions. f irst, ce turns on the control logic that allows access to the shift register for the address/command sequence. second, the ce signal provides a method of terminating either single - byte or multiple - byte ce data transfer. a clock cycle is a sequence of a rising edge followed by a falling edge. for data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. if the ce input is low, all data transfer terminates and the i/o pin goes to a high - impedance state. figure 4 shows data transfer. at power - up, ce must be a logic 0 until v cc > 2.0v. also, sclk must be at a logic 0 when ce is driven to a logic 1 state. data input following the eight sclk cycles that input a write command byte, a data byte is input on the ris ing edge of the next eight sclk cycles. additional sclk cycles are ignored should they ina dvertently occur. data is input starting with bit 0. data output following the eight sclk cycles that input a read command byte, a data byte is output on the falling edge of the next eight sclk cycles. note that the first data bit to be transmitted occurs on the f irst falling edge after the last bit of the command byte is written. additional sclk cycles retransmit t he data bytes should they inadvertently occur so long as ce remains high. this operation permits continuous burst mode read capabil ity. also, the i/o p in is tri - stated upon each rising edge of sclk. data is output starting with bit 0. burst mode burst mode can be specified for either the clock/calendar or the ram register s by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). as before, bit 6 specifies c lock or ram and bit 0 specifies read or write. there is no data storage capacity at locations 9 through 31 in the clock/calendar registers or l ocation 31 in the ram registers. reads or writes in burst mode start with bit 0 of address 0. when writing to the clock registers in the burst mode, the first eight registers must be wri tten in order for the data to be transferred. however, when writing to ram in burst mode it is not necessary to write all 31 byt es for the data to transfer . each byte that is written to will be transferred to ram regardless of whether all 31 b ytes are written or not. clock/calendar the time and calendar information is obtained by reading the appropriate register bytes. table 3 illustrates the rtc registers. the time and calendar are set or initialized by writing the appropr iate register bytes. the contents of the time and calendar registers are in the binary - coded decimal (bcd) format. the day - of - week register increments at midnight. values that correspond to the day of week are user - defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on.). illogical ti me and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of ce. the countdown chain is reset whenever the seconds register is written. write transfers occur on the falling edge of ce. to avoid rollover issues, once the countdown chain is reset, the remaining ti me and date registers must be written within 1 second. the ds1302 can be run in either 12 - hour or 24 - hour mode. bit 7 of the hours register is defined as the 12 - or 24 - hour mode - select bit. when high, the 12 - hour mode is selected. in the 12 - hour mode, bit 5 is the am/ pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the second 10 - hour bit (20 C 23 hours). the hours data must be re - initialized whenever the 12/ 24 bit is changed. 6 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p clock halt flag bit 7 of the seconds register is defined as the clock halt (ch) flag. when this bit is set to logic 1, the clock oscillator is stopped and the ds1302 is placed into a low - power standby mode with a current drain of less than 100na. when this bit is written to logic 0, the clock will start. the initial power - on state is not defined. write - protect bit bit 7 of the control register is the write - protect bit. the first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. before any write operation to the clock or ram, bit 7 must be 0. when high, the writ e - protect bit prevents a write operation to any other register. th e initial power - on state is not defined. therefore, the wp bit should be cleared before attempting to write to the device. trickle - charge register this register controls the trickle - charge characteristics of the ds1302. the simplified schematic of figure 5 shows the basic components of the trickle charger. the trickle - charge select (tcs) bits (bits 4 to 7) control the selection of the trickle charger. to prevent accidental enabling, only a pattern of 1010 enables the trick le charger. all other patterns will disable the trickle charger. the ds1302 powers up with the tr ickle charger disabled. the diode select (ds) bits (bits 2 and 3) select whether one diode or two diodes are connected between v cc2 and v cc1 . if ds is 01, one diode is selected or if ds is 10, two diodes are selected. if ds is 00 or 11, the trickle charger i s disabled independently of tcs. the rs bits (bits 0 and 1) select the resistor that is connec ted between v cc2 and v cc1 . the resistor and diodes are selected by the rs and ds bits as shown in table 2. table 2 . trickle charger resistor and diode select tcs bit 7 tcs bit 6 tcs bit 5 tcs bit 4 ds bit 3 ds bit 2 rs bit 1 rs bit 0 function x x x x x x 0 0 disabled x x x x 0 0 x x disabled x x x x 1 1 x x disabled 1 0 1 0 0 1 0 1 1 diode, 2k ? 1 0 1 0 0 1 1 0 1 diode, 4k ? 1 0 1 0 0 1 1 1 1 diode, 8k ? 1 0 1 0 1 0 0 1 2 diodes, 2k ? 1 0 1 0 1 0 1 0 2 diodes, 4k ? 1 0 1 0 1 0 1 1 2 diodes, 8k ? 0 1 0 1 1 1 0 0 initial power - on state diode and resistor selection is determined by the user according to the maximum current desired f or battery or super cap charging. the maximum charging current can be calculated as illustrated in the follow ing example. assume that a system power supply of 5v is applied to v cc2 and a super cap is connected to v cc1 . also assume that the trickle charger has been enabled with one diode and resistor r1 between v cc2 and v cc1 . the maximum current i max would therefore be calculated as follows: i max = (5.0v C diode drop) / r1 (5.0v C 0.7v) / 2k ? 2.2ma as the super cap charges, the voltage drop between v cc2 and v cc1 decreases and therefore the charge cu rrent decreases. 7 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p clock/calendar burst mode the clock/calendar command byte specifies burst mode operation. in this mode, the first eight c lock/calendar registers can be consecutively read or written (see table 3 ) s tarting with bit 0 of address 0. if the write - protect bit is set high when a write clock/calendar burst mode is specified, no data transf er will occur to any of the eight clock/calendar registers (this includes the control reg ister). the trickle charger i s not accessible in burst mode. at the beginning of a clock burst read, the current time is transferred to a second set of registers . the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re - read the registers in case of an update of the main registers during a read. ram the static ram is 31 x 8 bytes addressed consecutively in the ram address space. ram burst mode the ram command byte specifies burst mode operation. in this mode, the 31 ram registers can be consecutively read or written (see table 3 ) starting with bit 0 of address 0. register summary a register data format summary is shown in table 3. crystal selection a 32.768khz crystal can be directly connected to the ds1302 via pins 2 a nd 3 (x1, x2). the crystal selected for use should have a specified load capacitance (c l ) of 6pf. for more information on crystal selection and crystal layout consideration, refer to application note 58: crystal considerations for dallas real - time clocks . figure 4 . data transfer summary a1 a2 a3 a4 r/ c 1 ce sclk i/o r/ w a0 d1 d2 d3 d4 d5 d6 d7 d0 single - byte read a1 a2 a3 a4 r/ c 1 ce sclk i/o r/ w a0 d1 d2 d3 d4 d5 d6 d7 d0 single - byte write note: in burst mode, ce is kept high and additional sclk cycles are sent until the end of the burst . 8 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p table 3 . register address/definition rtc read write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 range 81h 80h ch 10 seconds seconds 00 C 59 83h 82h 10 minutes minutes 00 C 59 85h 84h 12/ 24 0 10 hour hour 1C 12/0 C 23 am /pm 87h 86h 0 0 10 date date 1C 31 89h 88h 0 0 0 10 month month 1C 12 8b h 8ah 0 0 0 0 0 day 1C7 8dh 8ch 10 year year 00 C 99 8fh 8eh wp 0 0 0 0 0 0 0 91h 90h tcs tcs tcs tcs ds ds rs rs clock burst bfh beh ram c1h c0h 00 - ffh c3h c2h 00 - ffh c5h c4h 00 - ffh . . . . . . . . . fdh fch 00 - ffh ram burst ffh feh figure 5 . programmable trickle charger 2k ? 4k ? 8k ? r1 r3 r2 v cc2 v cc1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charge register (90h write, 91h read) 1 0f 16 select note: only 1010b enables charger 1 of 2 select 1 of 3 select tcs 0-3 = trickle charger select ds 0-1 = diode select rout 0-1 = resistor select 9 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p absolute maximum ratings voltage range on any pin relative to ground. - 0.5vto +7.0v operating temperature range, commercial .0c to +70c oper ating temperature range, industrial (ind) - 40c to +85c storage temperature range ...- 55c to +125c soldering temperature (leads, 10 seconds)...260 c soldering temperature (su rface mount)...see ipc/jedec j - std - 020 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ar e stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated i n the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affec t device reliability. recommended dc operating conditions (t a = 0c to +70c or t a = - 40c to +85c.) (note 1) parameter symbol conditions min typ max units supply voltage v cc1 , v cc2 v cc1, v cc2 (notes 2, 10) 2.0 3.3 5.5 v logic 1 input v ih (note 2) 2.0 v cc + 0.3 v logic 0 input v il v cc = 2.0v (note 2) - 0.3 +0.3 v v cc = 5v - 0.3 +0.8 dc electrical characteristics (t a = 0c to +70c or t a = - 40c to +85c.) (note 1) parameter symbol conditions min typ max units input leakage i li (notes 5, 13) 85 500 a i/o leakage i lo (notes 5, 13) 85 500 a logic 1 output ( i oh = - 0.4ma) v oh v cc = 2.0v (note 2) 1.6 v logic 1 output (i oh = - 1.0ma) v cc = 5v 2.4 logic 0 output (i ol = 1.5ma) v ol v cc = 2.0v (note 2) 0.4 v logic 0 output (i ol = 4.0ma) v cc = 5v 0.4 active supply current (oscillator enabled) i cc1a v cc1 = 2.0v ch = 0 (notes 4, 11) 0.4 ma v cc1 = 5v 1.2 timekeeping current (oscillator enabled) i cc1t v cc1 = 2.0v ch = 0 (notes 3, 11,13) 0.2 0.3 a v cc1 = 5v 0.45 1 standby current (oscillator disabled) i cc1s v cc1 = 2.0v ch = 1 (notes 9, 11, 13) 1 100 na v cc1 = 5v 1 100 ind 5 200 active supply current (oscillator enabled) i cc2a v cc2 = 2.0v ch = 0 (notes 4, 12) 0.425 ma v cc2 = 5v 1.28 timekeeping current (oscillator enabled) i cc2t v cc2 = 2.0v ch = 0 (notes 3, 12) 25.3 a v cc2 = 5v 81 standby current (oscillator disabled) i cc2s v cc2 = 2.0v ch = 1 (notes 9, 12) 25 a v cc2 = 5v 80 trickle - charge resistors r1 2 k ? r2 4 r3 8 trickle - charge diode voltage drop v td 0.7 v 10 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p capacit ance (t a = +25c) parameter symbol min typ max units input capacitance c i 10 pf i/o capacitance c i/o 15 pf ac electrical characteristics (t a = 0c to +70c or t a = - 40c to +85c.) (note 1) parameter symbol conditions min typ max units data to c lk setup t dc v cc = 2.0v (note 6) 200 ns v cc = 5v 50 clk to data hold t cdh v cc = 2.0v (note 6) 280 ns v cc = 5v 70 clk to data delay t cdd v cc = 2.0v (notes 6, 7, 8) 800 ns v cc = 5v 200 clk low time t cl v cc = 2.0v (note 6) 1000 ns v cc = 5v 250 clk high time t ch v cc = 2.0v (note 6) 1000 ns v cc = 5v 250 clk frequency t clk v cc = 2.0v (note 6) 0.5 mhz v cc = 5v dc 2.0 clk rise and fall t r , t f v cc = 2.0v 2000 ns v cc = 5v 500 ce to clk setup t cc v cc = 2.0v (note 6) 4 s v cc = 5v 1 clk to ce hold t cch v cc = 2.0v (note 6) 240 ns v cc = 5v 60 ce inactive time t cwh v cc = 2.0v (note 6) 4 s v cc = 5v 1 ce to i/o high impedance t cdz v cc = 2.0v (note 6) 280 ns v cc = 5v 70 sclk to i/o high impedance t ccz v cc = 2.0v (note 6) 280 ns v cc = 5v 70 note 1: limits at - 40c are guaranteed by design and are not production tested. note 2: all voltages are referenced to ground. note 3: i cc1t and i cc2t are specified w ith i/o open, ce and sclk set to a logic 0. note 4: i cc1a and i cc2a are specified with the i/o pin open, ce high, sclk = 2mhz at v cc = 5v; sclk = 500khz, v cc = 2.0v. note 5: ce, sclk, and i/o all have 40k ? pulldown resistors to ground. note 6: measured at v ih = 2.0v or v il = 0.8v and 10ns maximum rise and fall time. note 7: measured at v oh = 2.4v or v ol = 0.4v. note 8: load capacitance = 50pf. note 9: i cc1s and i cc2s are specified with ce, i/o, and sclk open. note 10: v cc = v cc2 , when v cc2 > v cc1 + 0 .2v; v cc = v cc1 , when v cc1 > v cc2 . note 11: v cc2 = 0v. note 12: v cc1 = 0v. note 13: typical values are at +25c. 11 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chi p figure 6. timing diagram: read data transfer ce sclk i/o t dc t cdh t cc t cdz t cdd t r t f t cl t ch address/command byte read data byte t ccz figure 7. timing diagram: write data transfer ce sclk i/o t dc t cdh t cc t r t f t cl t cch t cwh address/command byte write data byte t ch chip information transistor count: 11,500 thermal information package theta - ja (c/w) theta - jc (c/w) 8 dip 110 40 8 so (150 mils) 170 40 package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . package type package code document no. 8 pdip 21 - 0043 8 so (208 mils) 21 - 0262 8 so (150 mils) 21 - 0041 12 of 13 downloaded from: http:///
ds1302 trickle - charge timekeeping chip revision history revision date description pages changed 120208 removed the leaded parts and references to the 16 - pin so package. 1, 4, 12 in the features section, changed the 31 x 8 ram feature to indicate that it is battery backed. 1 updated figure 1 and removed original figure 2 (oscillator circuit). 3, 5 added a new table 2 for the trickle charger resistor and diode select. 7 replaced the timing diagrams (figures 6 and 7). 12 added package information table. 12 3/15 updated benefits and features section 1 13 of 13 maxim/dallas semiconductor cannot assume responsibility for use of any circ uitry other than circuitry entirely embodied in a maxim/dallas semicon ductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and s pecifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 15 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. downloaded from: http:///

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